Register Bits

Twitpic from S_Tomasello "How's the attendance at #46DAC today? Umm..."

Last week at the Moscone Center in San Fransisco, the 46th annual Design Automation Conference (DAC) took place.  I’ve attended this conference for the past 4 years and decided not to attend this year.  This year I attended virtually using the web.

In the EDA media and for EDA trade shows, as Bob Dylan sang, the times they are a-changin’.  It’s no secret that the incumbent media is struggling to find a business model that works in the uncharted waters of the future.  As history repeats itself, the “hidden hand of supply and demand” will no doubt fix some shortfall with the traditional model — a shortfall that may not be fully understood until it is solved.

With the electronic media shedding their top writers, the coverage of DAC by trade publications is diminishing.  At the same time, new media, such as blogs, Twitter, and LinkedIn are picking up some slack.  For example, Richard Goering and Michael Santarini who historically covered DAC for EETimes and EDN now write for Cadence and Xilinx respectively.  Some of the best DAC summaries that I read were blogged by:

• Peggy Aycinena’s on her Thursday’s Child (R U a Wizard of Management Warcraft?)
• Mike Demler on his “The World is Analog” blog (Highlights from the Design Automation Conference, #46DAC - Day 1)
  
• Richard Goering on his Cadence blog (Ten Takeaways From the EDA CEO Panel, 8 Design Managers Reveal Top Concerns, GPUs Or Multicore For EDA Applications?)
• JL Gray’s Cool Verification (The Past, Present and Future of the DAC)
• Paul McLellan on his EDA Graffiti blog (day 1, VC Panel, denial computing)
• Sean Murphy at SKMurphy.com (provides a great index of blog postings on the 46th DAC)

Additionally, on Twitter, the #46DAC tag provided useful information about what was going on at the tradeshow.  For me, some tweeps who provided informative DAC coverage via Twitter included:

• Dark_Faust — editor in chief of Chip Design & Embedded Intel magazines & editorial director of Extension Media
• harrytheASICguy — ASIC consultant & blogger, did a Synopsys XYZ conversation central sessions at DAC
• jlgray — Consultant with Verilab, photographer, coolverification.com blogger, conference presenter
• karenbartleson — Sr. Director of Community Marketing at Synopsys and blogger on “The Standards Game.”  Karen won “EDA’s Next Top Blogger” at DAC.  Karen did a lot of tweeting to inform people about the #46DAC and Synopsys Conversation Central had a “Twitter Tower” that displayed the #46DAC stream.
• MikeDemler — Tech industry analyst, former marketing insider (from Synopsys), blogs at “The world is Analog”
• paycinera — EDA Confidential editor Peggy Aycinena broke her cryptic series of gobbledygook biography tweets, the EDA Town & Gown Twitter Project, to provide some of the best Twitter coverage from DAC
• S_Tomasello — Marketing at Sonics, the providers of “On-chip communications networks for advanced SoCs”

Based on the various reports and summaries from DAC, there is an apparent need for collaboration (as mentioned by keynote Fu-Chieh Hsu of TSMC) and productivity (as mentioned by the CEO panel). The same forces that are changing EDA trade media and conferences — the power of the Internet, coupled with economic forces –may enable the solution to better collaboration and productivity. Cloud computing business models like Infrastructure-as-a-Service (IaaS), Platform-as-a-Service (PaaS), and Software-as-a-Service (SaaS) are starting to prove themselves in other industries and will continue to find their way into commonplace. Exactly what the “hidden hand of supply and demand” has in store for EDA and cloud computing has yet to be revealed and we are just in the early stages now.

From various blogs and Twitter, without having attended DAC, I understand that:

• there continues to be a need for better collaboration, productivity, and higher levels of abstraction
• today’s current economic situation, spurred by the US credit melt-down, has affected EDA
  • the traditional trade media is struggling
  • new chip design starts are down
  • Magma design Automation, released that they are re-negotiating debt as a result of an audit report regarding their solvency, just as the conference was kicking off
  • traffic on the trade floor was questionable: some said it was above expectations while others said it was below
  • new VC investment in EDA start-ups is pretty much non-existent
  • TSMC is becoming more and more of an ecosystem heavyweight
  • there is optimism about the future and the recovery of EDA — with change and crisis, there comes opportunity for those who see it
• the media landscape is changing
  • there is a struggle between the blogsphere and traditional press to cover EDA
  • blogs are gaining acceptance and playing more and more of a role
  • filtering through and connecting disperse info is a problem
  • John Cooley dismisses the utility of blogging, LinkedIn and Twitter and critics say Cooley just doesn’t get it (or virtual platforms and virtual prototypes for that matter)
• there are big opportunities for Software design, and EDA can play there
  • Embedded software has the possibility to double EDA, says Gary Smith, who has pointed to software as the problem for several years now
  • embedded software seats are growing but market is fragmented
  • software IP is of growing importance in the differentiation of SoC platforms
  • the programming models need to change for multi-core
  • multi-core and parallel computing programming models are still pretty low level, like assembly and micro-code
  • Mentor Graphics announced their acquisition of Embedded Alley Solutions, a leader in Android and Linux development systems, unveiling their new Android & Linux strategy
• System Level is big, particularly for SoC virtual platforms, architectural optimization and IP
  • the SPIRIT Consortium and IP-XACT has merged into Accellera, and there continues to be a need for better standards
  • IP still has a lot of potential and the business model is becoming clearer
  • Despite the importance of ESL, much work is still done at lower levels of abstraction
  • ARC International, the IP and configurable processor provider, is rumored to be under acquisition
• FPGA
  • Companies are moving to FPGAs and away from ASIC
  • ESL is big for FPGAs
  • Not nearly as much FPGA discussion at DAC as there should be
• Cloud computing opportunities are being underlooked by EDA (let’s start with the on-site private cloud then look at multi-tenant ecosystem clouds)

In conclusion, I was able to absorb a lot of details about DAC without attending thanks to all the bloggers, Tweeters and trade media.  EDA is changing in some exciting ways that scream opportunity for some and failure for others, and that’s what makes the future so exciting.

While on an ocean side walk, I daydreamed of being struck by a great IP/subsystem idea with potential for royalty licensing.  I imagined organizing a team and jumping into action, developing the RTL logic, and processor integration.  Should I choose Virtual and/or FPGA prototyping?

ocean side walk

Virtual Platform

It’s all about getting the software working as soon as possible.  The Google Android Emulator is an excellent example of how Google was able to get the software working without requiring developers to possess the device hardware.  The Android Emulator is described as a “mobile device emulator — a virtual mobile device that runs on your computer.”  Android abstracts the hardware, ARM processor, and Linux kernel with an Eclipse based Java framework, targeting Android’s Dalvik Virtual Machine, a register-based architecture that’s more memory efficient than the Java VM.

Virtual Prototyping

Clearly the virtual Android emulator/platform makes software development easier. Similarly, a virtual prototype makes abstract product validation easier. With a virtual prototype, the developers can explore different algorithms and architectures across the hardware and software abstractions.  Things like instruction set, on-chip interconnect, acceleration, memory, interrupt, and caching architecture can be explored by digital designers and firmware ahead of the VHDL and Verilog solidification.  Still, despite any effort spent on virtual prototyping, physical validation is essential before offering an IP for license.  FPGA prototyping is a good choice for all but the most complex and highest performance IP.

FPGA Prototyping

Those who know firmware and RTL coding, should have no problem getting basic examples running on an FPGA dev kit in the first day or two.  Those with experience validating a chip in the lab understand that so much really comes down to using embedded software to drive the tests.  Today’s Embedded System FPGA kits provide on-chip processors and the whole development environment.  Some available embedded FPGA processor options are listed in the following table:

Short of having deep pockets for an ASIC flow, or a platform provider lined up to license the IP and spin prototype silicon, FPGA prototyping makes good sense.  Virtual platforms make sense for reaching software developers, so they can interface with the IP as soon as possible.  One problem with providing models for developing software before the hardware is complete is that it’s difficult to keep the different perspectives aligned as the design evolves.  Tools like SpectaReg that model hardware/software interfacing and auto-generate dependent code keep the different stakeholders aligned, resulting in quicker time to revenue for the IP.

So back to my oceanside daydream… how would I get the IP to market and start making money?  It depends on the target market.  If the end user targets embedded system FPGAs then it’s a no brainer - go straight to FPGA prototyping and don’t worry about virtual platform.  If the target market is mobile silicon platforms, then virtual prototyping/platforming makes sense.  Having validated silicon in hand is ideal but impractical in many circumstances. FPGA prototyping is pretty darn compelling when you consider the speedy turnaround times, and the low startup costs.