A quick snapshot on the poll described in my previous posting: “for System-on-Chip developers, where is the greatest hardware/software register interface pain?”
Of the 71 votes thus far, 59% indicated that synchronizing the firmware, RTL, hardware verification, and documentation was the greatest pain. Then 16% voted for register documentation and 16% for hardware verification (like SystemVerilog, Vera, e, SystemC). The RTL (like Verilog & VHDL) for coding the register-map hardware logic was a pain for 4% of voters and firmware was a pain for 2%. The live version of the poll is available here, and below is a screenshot of the graph.
That only 2% voted for firmware is surprising to me since when asked where greatest value was received, a SpectaReg.com register-map automation customer indicated that 50% of the value was provided to the firmware developer. As a result, I would expect that anyone without a register code generation solution would experience a lot of firmware pain. Perhaps that’s a synchronization pain and the proper solution provides more value for firmware than any other aspect as a result of cross-team synchronization.
For the 41% that did not vote for synchronization, perhaps they have no register map code generation solution, whether it be commercial or homemade. Perhaps their solution does not sufficiently provide enough value for the option that they voted for.
For the 59% that voted for synchronization, I wonder:
Many more polls could be created on these topics.
People are very passionate and opinionated when it comes to in-house tools, open source, register specification file formats, and register-map methodologies in general. There was heated discussions on LinkedIn about the following topics, which make for good future blog posts:
If you have thoughts to share, be sure to leave a comment for discussion. There is some good meat here for future RegisterBits.com postings so stay tuned.