Tag: embedded

In English Bay off West Point Grey in Vancouver lies an ideal spot for catching Dungeness Crabs - a wonderful delight to eat.  My first experience crabbing was dropping a trap off a friend’s boat en route to Chinook Salmon fishing in the Geogria Straight.  It’s not unusual to catch your limit on Spanish Banks if you know what you’re doing and to buy the equivalent at the local fish market will cost you almost $100.

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Dungeness Crabs

Dungeness Crabs

This summer some friends and I went out in Kayaks and were quite successful at catching our limits.  Google maps on the iPhone helped us to locate the trap after a paddle around the bay.  Being on the water with a 3G connected smartphone is pretty handy.

On another occasion, while trolling on a Salmon fishing mission after having dropped the trap, we pondered how many crabs had entered the trap. At the same time internet radio streamed care of the iPhone’s 3G internet. I got thinking how cool it would be if we had a 3G link to a web camera down below to show us what was inside.  Next thing you know I was drawing up plans for an autonomous crabbing vessel.

Continue reading…

Good news for the FPGA masses who want access to the ARM ecosystem of operating systems, tools, IP, and applications — last week Xilinx and ARM announced their collaboration to enable ARM processors and interconnect on Xilinx FPGAs.  This new dimension of the Xilinx Targeted Design Platform is a dramatic shift by Xilinx, away from their traditional IBM Power PC Architecture.

Meanwhile, over on Innovation Drive, Altera is licensing the MIPS architecture, and the market awaits more information.

Having an on-FPGA ARM is not a new idea. Early this decade Altera introduced their ARM-based hard core then changed strategy toward their NIOS II soft processor. And of course Actel, Altera and Xilinx have been supporting ARM-based soft cores for some time.

The announcement reveals that Xilinx is adopting “performance-optimized ARM cell libraries and embedded memories,”  conjuring images of ARM-based hard cores. They mention that the roadmap is toward “joint definition of the next-generation ARM® AMBA® interconnect technology… optimized for FPGA architectures.” This hints that the interconnect will be at least partially in the fabric as one would expect in an FPGA embedded system.   How the FPGA architect extends the base system and configures and stitches the fabric remains to be seen. With only vague bits of information released there are many unanswered questions:

  1. What does this mean to Xilinx’s customers using IBM PowerPC processor, MicroBlaze processor with IBM CoreConnect (PLB & OPB)?
  2. What is the tool chain?  Will ARM/AMBA be supported within Xilinx tools (like XPS & EDK) or is the community supported by a third party tool-chain?
  3. Which of the AMBA protocols will be supported by Xilinx — AXI, AHB and/or APB? AXI is the only one explicitly mentioned in the Xilinx Targeted Design Platforms boiler plate.
  4. Will the ARM RISCs be available as hard and/or soft cores within Xilinx FPGAs?  As stated earlier, my guess is that it’s a hard core.

If you have any hard answers or guesses about what’s going on here, please to leave a comment.

Personally, I’m exited to get PDTi engineering hands on an ARM-based Xilinx dev kit so we can help our customers continue to simplify their hardware/software register interface management should they choose ARM-based Xilinx embedded systems.

[UPDATE 2009-11-05]

From the comments there are some other great questions:

  • How will Xilinx’s strategy with ARM differ from that of Altera and what did Altera miss (if anything) in getting customers onto their ARM-based FPGA platform? [Gary Dare]
  • Why did Altera veer towards their own NIOS after going through all that trouble to get ARM-based products? [Gary Dare]
  • With MIPS as their alternative architecture, is Altera looking to horn in on QuickLogic’s market? [Gary Dare]
  • In what market will ARM FPGA platform offerings be the most successful? What market/application is Xilinx going to focus in on first?


Wow, what a spectacular run the equity markets have had since the low in March of 2009.  Meanwhile, the jury is out on whether this is a sustainable recovery, backed by fundamentals and precedent? There are people calling for hyperinflation and others for deflation ahead.  With such uncertainty, opinions vary widely regarding which way things will go as illustrated by the following articles which I found interesting (followed by my point form summaries):

The Greenback Effect
NT Times Opinion Article by Warren Buffett

  • “gusher of federal money” avoided meltdown & was needed to combat depression
  • “economy appears to be on a slow path to recovery”
  • US deficit/GDP will rise to 13% this year into uncharted territory - more than 2x the wartime record
    Continue reading…

Tweet from S_Tomasello Hows the attendance at #46DAC today? Umm...

Twitpic from S_Tomasello "How's the attendance at #46DAC today? Umm..."

Last week at the Moscone Center in San Fransisco, the 46th annual Design Automation Conference (DAC) took place.  I’ve attended this conference for the past 4 years and decided not to attend this year.  This year I attended virtually using the web.

In the EDA media and for EDA trade shows, as Bob Dylan sang, the times they are a-changin’.  It’s no secret that the incumbent media is struggling to find a business model that works in the uncharted waters of the future.  As history repeats itself, the “hidden hand of supply and demand” will no doubt fix some shortfall with the traditional model — a shortfall that may not be fully understood until it is solved.

With the electronic media shedding their top writers, the coverage of DAC by trade publications is diminishing.  At the same time, new media, such as blogs, Twitter, and LinkedIn are picking up some slack.  For example, Richard Goering and Michael Santarini who historically covered DAC for EETimes and EDN now write for Cadence and Xilinx respectively.  Some of the best DAC summaries that I read were blogged by:

Additionally, on Twitter, the #46DAC tag provided useful information about what was going on at the tradeshow.  For me, some tweeps who provided informative DAC coverage via Twitter included:

  • Dark_Faust — editor in chief of Chip Design & Embedded Intel magazines & editorial director of Extension Media
  • harrytheASICguy — ASIC consultant & blogger, did a Synopsys XYZ conversation central sessions at DAC
  • jlgray — Consultant with Verilab, photographer, coolverification.com blogger, conference presenter
  • karenbartleson — Sr. Director of Community Marketing at Synopsys and blogger on “The Standards Game.”  Karen won “EDA’s Next Top Blogger” at DAC.  Karen did a lot of tweeting to inform people about the #46DAC and Synopsys Conversation Central had a “Twitter Tower” that displayed the #46DAC stream.
  • MikeDemler — Tech industry analyst, former marketing insider (from Synopsys), blogs at “The world is Analog”
  • paycinera — EDA Confidential editor Peggy Aycinena broke her cryptic series of gobbledygook biography tweets, the EDA Town & Gown Twitter Project, to provide some of the best Twitter coverage from DAC
  • S_Tomasello — Marketing at Sonics, the providers of “On-chip communications networks for advanced SoCs”

Based on the various reports and summaries from DAC, there is an apparent need for collaboration (as mentioned by keynote Fu-Chieh Hsu of TSMC) and productivity (as mentioned by the CEO panel). The same forces that are changing EDA trade media and conferences — the power of the Internet, coupled with economic forces –may enable the solution to better collaboration and productivity. Cloud computing business models like Infrastructure-as-a-Service (IaaS), Platform-as-a-Service (PaaS), and Software-as-a-Service (SaaS) are starting to prove themselves in other industries and will continue to find their way into commonplace. Exactly what the “hidden hand of supply and demand” has in store for EDA and cloud computing has yet to be revealed and we are just in the early stages now.

From various blogs and Twitter, without having attended DAC, I understand that:

  • there continues to be a need for better collaboration, productivity, and higher levels of abstraction
  • today’s current economic situation, spurred by the US credit melt-down, has affected EDA
    • the traditional trade media is struggling
    • new chip design starts are down
    • Magma design Automation, released that they are re-negotiating debt as a result of an audit report regarding their solvency, just as the conference was kicking off
    • traffic on the trade floor was questionable: some said it was above expectations while others said it was below
    • new VC investment in EDA start-ups is pretty much non-existent
    • TSMC is becoming more and more of an ecosystem heavyweight
    • there is optimism about the future and the recovery of EDA — with change and crisis, there comes opportunity for those who see it
  • the media landscape is changing
    • there is a struggle between the blogsphere and traditional press to cover EDA
    • blogs are gaining acceptance and playing more and more of a role
    • filtering through and connecting disperse info is a problem
    • John Cooley dismisses the utility of blogging, LinkedIn and Twitter and critics say Cooley just doesn’t get it (or virtual platforms and virtual prototypes for that matter)
  • there are big opportunities for Software design, and EDA can play there
    • Embedded software has the possibility to double EDA, says Gary Smith, who has pointed to software as the problem for several years now
    • embedded software seats are growing but market is fragmented
    • software IP is of growing importance in the differentiation of SoC platforms
    • the programming models need to change for multi-core
    • multi-core and parallel computing programming models are still pretty low level, like assembly and micro-code
    • Mentor Graphics announced their acquisition of Embedded Alley Solutions, a leader in Android and Linux development systems, unveiling their new Android & Linux strategy
  • System Level is big, particularly for SoC virtual platforms, architectural optimization and IP
    • the SPIRIT Consortium and IP-XACT has merged into Accellera, and there continues to be a need for better standards
    • IP still has a lot of potential and the business model is becoming clearer
    • Despite the importance of ESL, much work is still done at lower levels of abstraction
    • ARC International, the IP and configurable processor provider, is rumored to be under acquisition
  • FPGA
    • Companies are moving to FPGAs and away from ASIC
    • ESL is big for FPGAs
    • Not nearly as much FPGA discussion at DAC as there should be
  • Cloud computing opportunities are being underlooked by EDA (let’s start with the on-site private cloud then look at multi-tenant ecosystem clouds)

In conclusion, I was able to absorb a lot of details about DAC without attending thanks to all the bloggers, Tweeters and trade media.  EDA is changing in some exciting ways that scream opportunity for some and failure for others, and that’s what makes the future so exciting.

While on an ocean side walk, I daydreamed of being struck by a great IP/subsystem idea with potential for royalty licensing.  I imagined organizing a team and jumping into action, developing the RTL logic, and processor integration.  Should I choose Virtual and/or FPGA prototyping?

English Bay, Oceanside

ocean side walk

Virtual Platform

It’s all about getting the software working as soon as possible.  The Google Android Emulator is an excellent example of how Google was able to get the software working without requiring developers to possess the device hardware.  The Android Emulator is described as a “mobile device emulator — a virtual mobile device that runs on your computer.”  Android abstracts the hardware, ARM processor, and Linux kernel with an Eclipse based Java framework, targeting Android’s Dalvik Virtual Machine, a register-based architecture that’s more memory efficient than the Java VM.

Virtual Prototyping

Clearly the virtual Android emulator/platform makes software development easier. Similarly, a virtual prototype makes abstract product validation easier. With a virtual prototype, the developers can explore different algorithms and architectures across the hardware and software abstractions.  Things like instruction set, on-chip interconnect, acceleration, memory, interrupt, and caching architecture can be explored by digital designers and firmware ahead of the VHDL and Verilog solidification.  Still, despite any effort spent on virtual prototyping, physical validation is essential before offering an IP for license.  FPGA prototyping is a good choice for all but the most complex and highest performance IP.

FPGA Prototyping

Those who know firmware and RTL coding, should have no problem getting basic examples running on an FPGA dev kit in the first day or two.  Those with experience validating a chip in the lab understand that so much really comes down to using embedded software to drive the tests.  Today’s Embedded System FPGA kits provide on-chip processors and the whole development environment.  Some available embedded FPGA processor options are listed in the following table:

Vendor/Processor On-chip interfaces Tools
Altera NIOS II

(soft core)

Avalon SOPC Builder

Quartus II

NIOS II IDE, with Eclipse CDT &

GNU compiler/debugger

Xilinx PowerPC

(hard core)

CoreConnect PLB & OPB Embedded Development Kit (EDK), with Eclipse CDT GNU compiler/debugger

Xilinx Platform Studio (XPS)


Xilinx MicroBlaze

(soft core)

CoreConnect PLB & OPB Embedded Development Kit (EDK), with Eclipse CDT GNU compiler/debugger

Xilinx Platform Studio (XPS)


Actel ARM

(soft core)

AMBA AHB & APB Libero IDE, CoreConsole, SoftConsole (Eclipse, GNU Compiler/debugger)

Short of having deep pockets for an ASIC flow, or a platform provider lined up to license the IP and spin prototype silicon, FPGA prototyping makes good sense.  Virtual platforms make sense for reaching software developers, so they can interface with the IP as soon as possible.  One problem with providing models for developing software before the hardware is complete is that it’s difficult to keep the different perspectives aligned as the design evolves.  Tools like SpectaReg that model hardware/software interfacing and auto-generate dependent code keep the different stakeholders aligned, resulting in quicker time to revenue for the IP.

So back to my oceanside daydream… how would I get the IP to market and start making money?  It depends on the target market.  If the end user targets embedded system FPGAs then it’s a no brainer - go straight to FPGA prototyping and don’t worry about virtual platform.  If the target market is mobile silicon platforms, then virtual prototyping/platforming makes sense.  Having validated silicon in hand is ideal but impractical in many circumstances. FPGA prototyping is pretty darn compelling when you consider the speedy turnaround times, and the low startup costs.

This is a technical posting for the firmware readership.

One of the most elegant ways of expressing register bit-fields in C/C++ firmware is using a union of a struct with a register word.  The problem with this is that there is no standard way for representing the bit field packing/ordering in C/C++, which restricts portability across compilers and architectures.  For the simple traffic light controller (TLC) example with the register-map shown here, the LightState Register’s Green, Amber and Red bit-fields can be represented as shown below, assuming most to least significant bit packing.

    struct {
        volatile unsigned : 29;
        volatile unsigned green : 1;
        volatile unsigned amber : 1;
        volatile unsigned red : 1;
    } fields;
    volatile u32 reg;

If the bit-order packing is reversed, then it needs to look as follows:

    struct {
        volatile unsigned red : 1;
        volatile unsigned amber : 1;
        volatile unsigned green : 1;
        volatile unsigned : 29;
    } fields;
    volatile u32 reg;

The reversal of the bit fields can be done using auto-generation based on a bit-ordering condition with a register automation tool like SpectaReg.  For non-generated static code, it can be accomplished using #ifdefs, and sometimes compiler pragmas.

The most portable way to deal with register bits in C/C++ is NOT to use this struct/union fanciness — instead do the required masking (and possibly shifting) using bitwise operators.  SpectaReg produces both the struct/union format and also the shift/mask format. How does the RegisterBits readership do it?

Did you know that LinkedIn allows users to create polls?  I discovered this today and created my first poll to ask my network of SoC developers where their greatest hardware/software register interface pain lies.  Is it the firmware, RTL, hardware verification, documentation, or is it synchronizing all the different perspectives around the common specification?

Click on the below image or link to have your say!  Tell your colleagues too, and of course if you have a comment for discussion post it here.


LinkedIn SoC Register Interface pain poll.


Update: Someone mentioned that they don’t understand the poll because they have an in-house solution that solves these pains. For those with an in-house solution, read the poll as “where is the greatest value from your in-house solution?” I suppose a sixth option, “my in-house solution is the biggest pain” should have also been an option too, especially now that there are commercial solutions available.

This posting examines how object-oriented typing of BitFields abstracts implementation details, and provides extensibility and simplicity.  This is the second in a series of postings.  The first posting provided background info on using object orientation for register specification and code generation.

With SpectaReg, one of the questions that always comes up is “how do I specify the type of register?”

How does one specify that a particular BitField is a read-only status bit, vs. a read-write flop-based control BitField vs. some other type?  With the SpectaReg register generation tool…

  1. Register type selection is easily done using the web GUI (or through XML)
  2. Register typing is generally done at a BitField-level of granularity
  3. Types are defined in an object oriented hierarchy
  4. Types can have custom attributes including references to other instances
  5. New types/classes can easily be added with some open Python
  6. The code generation layer works at the most abstract level that is applicable, to maximize core reuse (thanks to inheritance and polymorphism)

A clarifying example:

To keep things simple, assume an SoC team only uses three types of BitFields in their register maps as defined by the following table.  In reality there would be many more types.

Type Name Type Description
ExportedFlopBitField A basic read/write control BitField.  This is implemented with flip-flops and has an output wire/signal from the register module that goes into the application specific logic.
WatchedExportedFlopBitField Same as the ExportedFlopBitField except this has an additional output wire/signal that goes into the application specific logic and pulses high when a write transaction is decoded.
ExtDrivenBitField A basic read only status BitField.  This is an input into the register module from the application specific logic.

Now, in SpectaReg’s Specification Object Model (SOM) these types of BitFields would be mapped into the following class hierarchy, all inheriting from the BitField base class (i.e. the IP-XACT field element).

Register BitField Class Hiearchy

Register BitField Class Hierarchy

The WatchedExportedFlopBitField is a specialized type of ExportedFlopBitField, which is a type of ReadWriteBitField, which is a FlopBitField, which is a type of BitField.  As is typical for object orientation, “is a” represents inheritance relationships.

Say the user wants to create a new WatchedExportedFlopBitField in an unused bit-space of an existing register.  The user would create a new BitField and tag it with the specific WatchedExportedFlopBitField class using the GUI widget shown in the following screen shot.

BitField Class/Type Selection Widget

BitField Class/Type Selection Widget

At the code generation layer, such inheritance-based typing really simplifies things.  For creating the synthesizable Verilog and VHDL RTL code, the generation layer needs to know specific class typing to create the implementation of the WatchedExportedFlopBitField.  For the firmware and documentation generation, such detail is not required, so the code generation can work at a more abstract ReadWriteBitField classification level.  This is the beauty of polymorphism — the code-generation templates that need specifics can get into the details whereas the ones that don’t can keep it simple.  Keeping it abstract leads to more re-use and less complexity.

Of course, SpectaReg supports many different types/classes of BitFields other than those dicsussed here.  What Register and BitField types do you use in your design?

Register interfaces are an essential pattern in chip design. They provide a way for sequential software to get information into and out of parallel hardware using memory address reads and writes. At conference many years ago (can’t recall if it was DAC or DesignCon) a panel was asked “what is the best way to measure the complexity of a chip?” One proxy mentioned was “the number of pages in the user documentation.” The register section is often the majority of the firmware programmers’ manual… confirming what you probably know… register interfaces are complex in a variety of dimensions.  For the average hardware RTL coder, the register interface is typically not viewed as an object oriented model.  We believe that IT SHOULD BE!

In the center of the `School of Athens by Raphael are Aristotle and Plato, Aristotles hand level to the Earth symbolizing his realism view of Nature; Platos hand pointed towards the heaven symbolizing the mystical nature to his view of the Universe. This image symbols the sharp change in the meaning of how `natural philosophy or physics will be done for the 2,200 years.

In the center of the `School of Athens' by Raphael are Aristotle and Plato, Aristotle's hand level to the Earth symbolizing his realism view of Nature; Plato's hand pointed towards the heaven symbolizing the mystical nature to his view of the Universe. This image symbols the sharp change in the meaning of how `natural philosophy' or physics will be done for the 2,200 years.

Object Oriented Programming (OOP) is well known for its ability to abstract complexity. A quote from Grady Booch (co-founder of Rational Software, IBM Fellow, and widely respected authority on software methodology) puts this into perspective:

… objects for me provide a means for dealing with complexity. The issue goes back to Aristotle: do you view the world as processes or as objects? Prior to the OO movement, programming focused on processes — structured methods for example. However, that system reached a point of complexity beyond which it could not go. With objects, we can build bigger, more complex systems by raising the level of abstraction — for me the real win of the object-oriented programming movement.[source]

If you took CompSci 101 you may have learned about the following principles of OOP:

  • Inheritance - Classes of objects can be extended and specialized to reuse and override existing code.  For example, an InterruptBitfield inherits from BitField to extend it to have specific attributes and behaviour.
  • Encapsulation - Classes of objects have data and methods that they encapsulate.  For example, a BitField has a bitWidth attribute.
  • Polymorphism - Specific classes of objects should be able to play general roles.  For example, an InterruptBitField instance can also play the role of a general BitField

Certainly most SystemVerilog users for design verification will be familiar with OOP, but I’m not sure about the RTL camp.

In building a data structure for modeling the hardware register interface, an OOP language is preferred. We chose Python since it’s interpreted with decent object orientation.  It’s encouraging to hear that python is one of the 3 “official languages” at Google, alongside C++ and Java.

Another consideration with register automation, is how the specifications get persisted and exchanged? We were asking ourselves this question in 2004 when we learned of the SPIRIT Consortium which has a standard now know as IP-XACT, a XML Schema Definition (XSD) for SoC and IP metadata.  For OOP based register specification, we infer from IP-XACT the classes of objects shown in the following SpectaReg Specification Object Model (SOM) diagram.  The diagram is a UML class diagram that uses UpperCamelCase for defining the classes.  We’ll use this convention for referencing classes in this blog.

Specification Object Model (SOM) base classes from IP-XACT

Specification Object Model (SOM) base classes from IP-XACT

This diagram of the SOM doesn’t show the new RegisterFile class of object which we’ll talk about another time.

In English the diagram reads as follows: A Component is composed of MemoryMaps which are composed of AddressBlocks, which are composed of Registers, which are composed of BitFields.  Or in the other direction BitFields exist within Registers, and so on.

There are many different “types” of Registers in the universe of hardware/software Register interface specifications. The type of a Register’s contained BitFields specifies how the Register behaves in software and hardware. Such granular typing permits BitFields in the same Register to have different types.

We’ll continue this discussion in an upcoming posting to illustrate how the SOM simplifies the complexity of register implementation for both RTL and software engineers.  This exists today at SpectaReg.com without requiring the user to write or install any software or feed any code into the register automation tool.

I met Gary Stringham, an embedded systems consultant, at the 45th DAC SPIRIT Consortium meeting in Anaheim where we demonstrated the SpectaReg web-app using IP-XACT.  Since then, I’ve been subscribing to Gary’s excellent Embedded Bridge monthly newsletter, which provides best practices for the hardware/firmware divide.  Gary is a big proponent for register module generation tools like SpectaReg and he recommends such tools as one of his best practices.

Issue #26, of the Embedded Bridge newsletter discusses level-triggered vs. edge-triggered interrupts and makes a good case for using edge-triggered interrupts. Why?  Well, because level-triggered interrupts are painful for the firmware engineer.  Level-triggered interrupts cause extra complexity, extra CPU cycles, and create a possibility for missed interrupts.

Consider the following example…

Imagine you are creating a packet receiver (PR) hardware component. When the PR processes an errored packet, it asserts a status signal (pkt_err_stat) until the next packet comes in. The following table shows the PR’s register bits, which are mapped into addressable registers and are all one bit wide.

Bit Name Access Bit Description
has_int Read Only The PR component has an outstanding interrupt. Read all of the PR component’s interrupt bits to determine the source.
pkt_err_stat Read Only When 1, the PR’s current packet is in error, when 0, the current packet does not have an error.  For each new packet this will always be 0 for at least one cycle.
pkt_err_int_en Read/Write Write 1 to enable the packet error interrupt (pkt_err_int), write 0 to disable/mask the said interrupt.
pkt_err_int Read/Write When 1 an errored packet has been observed. Write 1 to clear this interrupt event.  [Also, describe here whether this is edge or level sensitive.]

When pkt_err_stat is asserted, an interrupt is generated (if enabled).   The interrupt causes firmware to vector to it’s interrupt handler, where it identifies that PR has an interrupt (since has_int for PR is asserted).  Firmware then reads PR’s interrupts to discover that pkt_err_int is asserted.

Level-triggered case: In the case where pkt_err_int is level-triggered and the next packet has yet to be received, then pkt_err_stat will still be asserted.  To exit the interrupt handler, the firmware must disable then clear the interrupt by writing one to it.  The issue now is… when does firmware re-enable the interrupt?  With the interrupt disabled, how does firmware know if the next packet is errored?  Answering these questions from firmware creates un-needed complexity.

Edge-triggered case: If pkt_err_int is an edge-triggered interrupt, then the firmware is simpler and less prone to missing back-to-back errored packets.  To exit the interrupt handler, the firmware simply clears the interrupt.  When the next packet comes in, if it’s errored another interrupt is generated and there is less risk of missing this event.

One objection to edge triggered interrupts, as Gary points out, is that they take up more logic gates.  When I read Gary’s level vs. edge triggered Embedded Bridge issue, I decided to look at SpectaReg’s generated VHDL and Verilog to see how we did our interrupts.  It turns out that we originally only had level-triggered interrupts.  To add support for positive edge-triggered interrupts, the RTL was pretty much identical to the level-triggered, it just required sampling the last value of the status (pkt_err_stat in the example) and using that to determine when to generate the interrupt. If the current value is 1 and the last value was 0 then the interrupt is generated.  This results in one additional flop per edge-triggered interrupt and a little more combinational logic.  The cost is insignificant compared to the benefit.

So…. all you Verilog and VHDL RTL developers, next time you go to create an interrupt bit do the firmware developer a favor and make it edge triggered.